Progress log #2

Posted on January 30, 2011

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Recently I realized that to complete this project in a sane amount of time (that is, short enough to satisfy my magpie-like attention span) I need to radically lower my standards. Here are a few stats:

  • 2-bits of computation (with signs!).
  • 3×2 RAM memory (that is, two bit integers with sign bits).
  • “Cartridge” ROM memory, capable of holding 4 instructions.
  • 2-bit Opcode, two addressing modes (literal and memory), three operands (A, B, and destination (where to put the result)).
  • 4 instructions (No operation (NOP), Add (ADD), NAND (NAN), and Jump-if-not-zero (JNZ))
  • Two registers, which are memory-mapped to the keypad and binary readout. I don’t suppose there’ll be much use of I/O, but it’s neat nonetheless.

I reasoned that every math operation is reducible to addition, every logic operation is reducible to NAND, JNZ is pretty utilitarian as control operations go, and no operation is required to fill up empty ROM space. Thus is my instruction set. Since it supports looping and conditional branching, it’s turing complete, too.

Think of this as a “pre-release” version of the OMH CPU, or rather, version 0. Once this design is fully constructed, I’ll have the motivation I need to build my initial design, OMH CPU v1.

Soooo…after rebuilding the ALU and RAM to meet these ridiculous “requirements”, I built the very first ROM chip for my computer. It’s only one instruction long, written to add 1+1 and store it in memory location 00. Now I’ll have to build the program counter and control unit.

Oh, and I’m afraid I can’t show any screenshots because my computer is having a spaz attack about how much memory my logic gate simulator is using up, so I had to close the program. We’ll see about it after a reboot.

Stay smart, folks.

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Posted in: OMH CPU