After seeing the wonderful projects on the home-brew CPU webring a couple of months ago, I decided that it would be a neat if practically infeasible project to use the logic gate simulator on my PC to construct my own CPU. This decision was long before the inception of this blog, but I admit I have had little time to spend on it.
The computer will be named the OMH CPU (look at the post title). It will be a 4-bit machine, have 16 bits of RAM (2 bytes), and enough ROM to hold about 16 instructions (still working on the instruction set and how that works out so I can’t say in advance how many bits). It will have two registers, one for the program counter and one for loading data from RAM. Oh, and it will use a bit-slice ALU.
I have since made a working RAM that has 16 bits and a 4-bit word size. Here’s how it looks:
The smaller macros arranged in a matrix in the center are the Data latches. The inputs at the left are (in order from top to bottom):
- Read/Write (off equals read, on equals write)
- The address (only needs two bits because there’s only four memory locations).
- The data to write.
The large macros at the right control reading. Basically, they OR together their respective bit of each address and check if the RAM is in read mode.
I have also made a bit-slice ALU with a 3-bit function code:
The inputs at the left are as follows:
- Not really important, I just call it the Sub Enabler because it’s sole purpose is to make the subtract function work properly.
- The function select.
- Data A (first operand).
- Data B (second operand).
The menagerie of smaller macros are the bitwise operations (ADD, AND, etc.). The huge macro is the multiplexer.
That’s the extent of work I’ve done on the OMH CPU. I plan to next make the program counter and maybe the ROM (which due to how much larger it is I’m sure will be tedious).